A liquid crystal display apparatus (LCD), featured by thin thickness, light weight and low power consumption, has recently come into widespread use, and is being predominantly used as a display for mobile equipment, such as portable telephone sets (mobile phones or cellular phones), PDA (Personal Digital Assistant), mobile information terminals or notebook PCs. In these days, the technique for enlarging the screen size or for coping with moving pictures has made progress such that it is possible nowadays to implement not only mobile equipment but also a stationary large screen display apparatus or a large screen liquid crystal TV. For such liquid crystal display apparatus, a liquid crystal display apparatus of the active matrix driving system, capable of high definition display, is currently used.
Referring to FIGS. 7A and 7B, an illustrative arrangement of a liquid crystal display apparatus of the active matrix driving system will be briefly described. FIG. 7A is a block diagram showing essential portions of a liquid crystal display apparatus, and FIG. 7B is a diagram showing essential portions of a unit pixel of a display panel of a liquid crystal display apparatus. In FIG. 7B, a unit pixel is schematically shown as an equivalent circuit.
Referring to FIG. 7A, a thin type display apparatus of the active matrix driving system includes a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970 and a data driver 980. The display panel 960 includes a matrix array of a plurality of unit pixels, each of which includes a pixel switch 964 and a display element 963. In the case of a color SXGA (Super eXtended Graphics Array) panel, for example, the matrix array includes 1280×3 pixel columns by 1024 pixel rows. On the display panel 960, a plurality of scan lines 961 that transmit scan signals output from the gate driver 970 to respective unit pixels and a plurality of data lines 962 that transmit gray scale voltage signals output from the data driver 980 are arranged in a lattice configuration. The gate driver 970 and the data driver 980 are controlled by the display controller 950. For example, clock signals CLK or control signals as needed are supplied by the display controller 950, and image data is supplied as digital signal to the data driver 980. The power supply circuit 940 supplies necessary supply power to the gate driver 970 and to the data driver 980. The display panel includes a semiconductor substrate. For a large screen display apparatus, in particular, a semiconductor substrate configured by an insulating substrate, formed of glass or plastics, is extensively used. The substrate includes a plurality of thin film transistors (TFTs), as pixel switches, formed thereon.
In the display apparatus, the on/off (conduction/non-conduction) of the pixel switch 964 is controlled by a scan signal. When the pixel switch 964 is turned on (rendered electrically conductive), a gray scale voltage signal, corresponding to the pixel data, is supplied to the display element 963. The display element 963 then is changed in luminance in response to the gray scale voltage signal, thus displaying a picture.
Each data equivalent to a single screen image is updated for each frame period which is usually about 0.017 sec for 60 Hz driving. Each scan line 961 selects (turns on) the pixel switch 964 from one pixel row to another, i.e., line-by line. During the time the pixel row is so selected, the gray scale voltage signal is supplied from each data line 962 via the pixel switch 964 to the display element 963. There are cases where a plurality of pixel rows is simultaneously selected by the scan line, or where the driving is by the frame frequency higher than 60 Hz.
Referring to FIGS. 7A and 7B, the liquid crystal display apparatus includes the display panel 960 including a semiconductor substrate, an opposite substrate, arranged facing the semiconductor substrate, and liquid crystal sealed in a gap between the two substrates. The semiconductor substrate has a matrix array of the pixel switches 964 and transparent pixel electrodes 973 as unit pixels. The opposite substrate has a single transparent electrode 974 extending on its entire surface. The display element 963, forming a unit pixel, includes the pixel electrode 973, the opposite substrate electrode 974, a liquid crystal capacitance 971 and an auxiliary capacitance 972. A backlight, not shown, is provided as a light source on a back side of the display panel.
When the pixel switch 964 is turned on (electrically conductive) by the scan signal from the scan line 961, a gray scale voltage signal from the data line 962 is applied to the pixel electrode 973. The backlight, transmitted through the liquid crystal, has its transmittance changed due to the potential difference between each pixel electrode 973 and the opposite substrate electrode 974. The potential difference is kept for certain time duration by the liquid crystal capacitance 971 and the auxiliary capacitance 972, even after the pixel witch 964 is turned off, thus providing a display.
It is noted that, in driving the liquid crystal display apparatus, the voltage polarity is reversed on a per pixel basis between plus and minus polarities with respect to the common voltage (COM) of the opposite substrate electrode 974 (inversion driving), usually every frame period, in order to prevent deterioration of the liquid crystal. As typical scheme for data line driving includes dot inversion driving where voltage polarities are made to differ between neighboring pixels, and column inversion driving where voltage polarities are made to differ between neighboring data lines. In the dot inversion driving, gray scale voltage signals of the polarities different from one selection period (one data period) to another are output to the data line 962. In the column inversion driving, gray scale voltage signals of the polarities which are the same from one selection period (one data period) to another are output to the data line 962 (In the column inversion driving, polarity inversion occurs every frame period).
FIG. 8 corresponds to FIG. 6 of Patent Document 1. As for details, reference may be made to the corresponding description of Patent Document 1. A differential stage 14 includes NMOS transistors MN11, MN12, MN13, MN15 and MN16, PMOS transistors MP11, MP12, MP13, MP15 and MP16, constant current sources 111 and 112, a floating current source 113 and switches SW11 and SW12. The NMOS transistors MN 11 and MN12, that have gates connected to a switch circuit 6 and an input terminal 12, respectively, composes an Nch differential pair. The constant current source 111, supplied with a negative power supply VSS, supplies a bias current to Nch differential pair transistors (NMOS transistors MN 11 and MN12). The PMOS transistors MP11 and MP12, that have gates connected to the switch circuit 6 and to the input terminal 12, respectively, compose a Pch differential pair. The constant current source 112, supplied with a positive power supply VDD, supplies a bias current to the Pch differential pair transistors (PMOS transistors) MP11 and MP12. The gates of the NMOS transistor MN 11 and the PMOS transistor MP11 are connected by the switch circuit 6 to an output terminal 11 or to an output terminal 21.
The PMOS transistors MP15 and MP16 have coupled sources connected to a power supply terminal 15 (positive power supply terminal voltage VDD), have drains connected respectively to the drains of the Nch differential pair transistors (NMOS transistors MN11 and MN12). The drain of the PMOS transistor MP15 is connected via switch SW11 and PMOS transistor MP13 to the floating current source 113. The gates of the PMOS transistors MP15 and MP16 are connected common to the floating current source 113 and to the drain of the PMOS transistor MP13. The PMOS transistors MP15 and MP16 thus operate as a folded cascode-connected active load. A bias voltage BP2 is supplied to the gate of the PMOS transistor MP13.
The NMOS transistors MN15 and MN16 have coupled sources connected to a power supply terminal 16 (negative power supply voltage VSS), have drains connected respectively to drains of Pch differential pair transistors (PMOS transistors MP11 and MP12). The drain of the NMOS transistor MN15 is connected via the switch SW12 and the NMOS transistor MN13 to the floating current source 113. The gates of the NMOS transistors MN15 and MN16 are connected in common to the floating current source 113 and to the drain of the NMOS transistor MN13. The NMOS transistors MN15 and MN16 thus operate as a folded cascode-connected active load. A bias voltage BN2 is supplied to the gate of the NMOS transistor MN13. The switches SW11 and SW12 are normally in an ON (conductive) state.
The drains of the NMOS transistor MN12 and the PMOS transistor MP16 are connected to an input stage output terminal 51, and are connected via switches SW51 and SW52 to an output stage 13 (source of PMOS transistor MP14) and to an output stage 23 (source of PMOS transistor MP24). The drains of the PMOS transistor MP12 and the NMOS transistor MN16 are connected to an input stage output terminal 52, and connected via switches SW53 and SW54 to the output stage 13 (source of NMOS transistor MN14) and to the output stage 23 (source of NMOS transistor MN24). In the above configuration, two input stage output signals Vsi11 and Vsi12, which are in accordance with an input signal Vin1, supplied to the input terminal 12, are output from the drains of the NMOS transistor MN12 and the PMOS transistor MP16 (input stage output terminal 51) and from the drains of the PMOS transistor MP12 and the NMOS transistor MN16 (input stage output terminal 52).
A differential stage 24 is configured in similar manner. However, for NMOS transistors MN11 to MN16, PMOS transistors MP11 to MP16, constant current sources 111 and 112, floating current source 113, switches SW11 and SW12, switches SW51 to SW54, bias voltages BP12 and BN12, input stage output terminals 51 and 52 and input stage output signals Vsi11 and Vsi12, read NMOS transistors MN21 to MN26, PMOS transistors MP21 to MP26, constant current sources 121 and 122, floating current source 123, switches SW21 and SW22, switches SW55 to SW58, bias voltages BP22 and BN22, input stage output terminals 53 and 54 and input stage output signals Vsi21 and Vsi22, respectively.
The differential stage 14 (24) has two differential pairs that receive the input signal Vin1 (Vin2). Each of the differential pairs includes a folded cascode-connected active load. The two differential pairs and active loads are configured by transistors of respective different conductivity types. Hence, two input stage output signals Vi11 and Vi12 (Vi21 and Vi22), which are supplied from the differential stages 14(24) to the output stage 13 or 23, are in-phase signals having different input levels.
In the differential stage 14 (24), when the voltage ranges of the input signals Vin1 (Vin2) are VSS to VDS(sat)+VGS, only the Pch differential pair (PMOS transistors MP11 and MP12 (MP21 and MP22)) is in operation. When the voltage ranges are (VDS(sat)+VGS to VDD−(VDS)(sat)+VGS), the Pch differential pair (PMOS transistors MP11 and MP12 (MP21 and MP22)) and the Nch differential pair (NMOS transistors MN11 and MN12 (MN21 and MN22)) are in operation. When the voltage ranges are (VDD−(VDS(sat)+VGS) to VDD), only the Nch differential pair (NMOS transistors MN11 and MN12 (MN21 and MN22)) is in operation. It is noted that VDS(sat) is a drain-to-source voltage at the change-over point of a tripod region and a pentode region of each of transistors that composes the constant current sources 111 and 112 (121 and 122), and VGS is a gate source voltage of each of the transistors that compose the differential pair (NMOS transistors MN11 and MN12 (MN21 and MN22) and the PMOS transistors MP11 and MP12 (MP21 and MP22)). As a result, the differential stages 14 and 24 operate rail-to-rail within the total voltage range of the input voltage of from VSS to VDD.
The output stage 13 dedicated to a positive-polarity, includes NMOS transistors MN14, MN17, and MN18, PMOS transistors MP14, MP17, and MP18 and phase compensation capacitances C1 and C2. The PMOS transistor MP17 and the NMOS transistor MN17 have drains coupled together, have sources also coupled together. In addition, bias voltages BP11 and BN11 are supplied to the gates of the transistors MP17 and MN17, which operate as a floating current source. The PMOS transistor MP14 has a gate connected to a constant bias voltage source (bias voltage BP12), and has a drain connected to one end of the floating current source (PMOS transistor MP17 and the NMOS transistor MN17). The NMOS transistor MN14 has a gate connected to a constant bias voltage source (bias voltage BN12), and has a drain connected to the other end of the floating current source (PMOS transistor MP17 and the NMOS transistor MN17). The PMOS transistor MP14 has a source connected via phase compensation capacitance C11 to the output terminal 11. The NMOS transistor MN14 has a source connected via phase compensation capacitance C12 to the output terminal 11.
The PMOS transistor MP18 has a drain connected to the drain of the NMOS transistor MN18 via the output terminal 11. The PMOS transistor MP18 has a gate connected to one end of the floating current source (and to the drain of the PMOS transistor MP 14), and has a source connected to the power supply terminal 15 (positive power supply terminal voltage VDD). The NMOS transistor MN18 has a gate connected to the other end of the floating current source (and to the drain of the NMOS transistor MN 14), and has a source connected to a power supply terminal 17 supplied with a power supply voltage VML.
The output stage 23 dedicated to a negative-polarity, is configured in similar manner. However, for NMOS transistors MN14, MN17 and MN18, PMOS transistors MP14, MP17 and MP18, phase compensation capacitances C11 and C12, power supply terminal 15 (positive power supply terminal voltage VDD), power supply terminal 17 (power supply voltage VML) and bias voltages BP11, BP12, BN11 and BN12, read NMOS transistors MN24, MN27 and MN28, PMOS transistors MP24, MP27 and MP28, phase compensation capacitances C21 and C22, power supply terminal 16 (negative power supply terminal voltage VSS), power supply terminal 18 (power supply voltage VMH) and bias voltages BP21, BP22, BN21 and BN22, respectively.
A switch SW61 controls connection between the output terminal 11 and the differential stage 14 (NMOS transistor MN11 and PMOS transistor MP11). A switch SW62 controls connection between the output terminal 11 and the differential stage 24 (NMOS transistor MN21 and PMOS transistor MP21). A switch SW63 controls connection between the output terminal 21 and the differential stage 24 (NMOS transistor MN21 and PMOS transistor MP21). A switch SW64 controls connection between the output terminal 21 and the differential stage 14 (NMOS transistor MN11 and PMOS transistor MP11).
The input transistors of the output stage 13 (PMOS transistor MP14 and NMOS transistor MN14) and the output transistors thereof (PMOS transistor MP18 and NMOS transistor MN18) are arranged symmetrically with respect to the output terminal 11. In similar manner, the input transistors of the output stage 23 (PMOS transistor MP24 and NMOS transistor MN24) and the output transistors thereof (PMOS transistor MP28 and NMOS transistor MN28) are arranged symmetrically with respect to the output terminal 21. The output stage 13 outputs a single-ended signal, which is produced based on two input-stage output signals Vsi11 and Vsi12, which are in phase with but differ in input level from each other, as an output signal Vout1 at the output terminal 11. In similar manner, the output stage outputs a single-end signal, which is produced based on two input-stage output signals Vsi21 and Vsi22, which are in phase with but differ in input level from each other, as an output signal Vout2 at the output terminal 21. It is noted that idling currents of the output transistors (PMOS transistor MP18 and NMOS transistor MN18) are determined by the bias voltages BP11 and BN11.
The arrangement of FIG. 8 is a half VDD amplifier, i.e., an amplifier whose driving power supply is provided for each of a positive-polarity dynamic range and for a negative-polarity dynamic range. The amplifier includes differential stages 14 (24) and output stages 13 (23). There are cases wherein, for the power supply voltage range of the differential stage 14 of VDD to VSS (VDD to VSS), the power supply voltage range of the output stage 13 is small and is VDD to VML, and wherein, in similar manner, for the power supply voltage range of the differential stage 24 of VDD to VSS, that of the output stage 23 is small and is VMH to VSS. For example, VML=VMH=VDD/2.
In driving a heavy load, such as that on a data line, at a high speed (for example, column inversion driving), the differential stage 14 is connected to the output stage 13 so that the positive polarity input voltage (Vin1) is applied to the differential stage 14, while the differential stage 24 is connected to the output stage 23 so that the negative polarity input voltage (Vin2) is applied to the differential stage 24. In case a positive polarity input voltage in the vicinity of the VDD power supply voltage is applied to the differential stage 14, with the output terminal being charged towards the VDD power supply voltage, the gate voltages of the transistors MP18 and MN18 of the output state 13 are transiently markedly lowered to the vicinity of the VSS power supply voltage which is lower than the intermediate power supply voltage VML. In this state, responsive to the change of the positive polarity input voltage towards the lower voltage side, for example, to the vicinity of VML, the NMOS transistor MN18 is not turned on until the gate voltages of the output stage transistors MP18 and MN18 are reverted to a value at which the output is in a stabilized state, and which is higher than VML. There occurs no changing over to the discharge operation, as a result of which there is produced a delay in the output signal voltage. In similar manner, in case a negative polarity input voltage in the vicinity of the VSS power supply voltage is applied to the differential stage 24, and the gate voltages of the output stage transistors MP28 and MN28 of the output stage 23 are appreciably increased to the vicinity of the VDD power supply voltage, with the change of the negative polarity input voltage towards the high voltage side, for example, to the vicinity of VMH, there is produced delay in the output signal voltage.
On the other hand, when the positive polarity input voltage in the vicinity of the power supply VML is applied to the differential stage 14, the gate voltages of the output stage transistors (MP18 and MN18) of the output stage 13 rise only to the vicinity of VDD. In this state, with the change of the positive polarity input signal to the VDD side, the gate voltages of the output stage transistors (MP18 and MN18) quickly revert to the voltage at which the output is in a stabilized state. The gate voltage of the output stage transistor MP18 continues to be lowered quickly to switch to the discharging operation. Thus, a delay of the output signal is scarcely produced. In similar manner, when the negative polarity input voltage in the vicinity of the power supply VMH is applied to the differential stage 24, the gate voltages of the output stage transistors MP28 and MN28 of the output stage 23 are lowered only to the vicinity of the VSS power supply voltage. In this state, with the change of the negative polarity input voltage towards the VSS side, a delay of the output signal voltage is scarcely produced.
FIG. 9 is re-drafted from FIG. 4 of Patent Document 2, in which the reference numerals are changed in re-drafting. Referring to FIG. 9, a positive polarity amplifier 210 includes a differential input stage, an intermediate stage and an output stage. The differential input stage of the positive polarity amplifier 210 includes a differential unit 210A including a current source M15 that has a first terminal connected to a low voltage source VSS, and an Nch differential pair (M11 and M12) that has coupled sources connected to the second terminal of the current source M15, and a Pch current mirror (M13 and M14). The Pch current mirror is connected between an output pair of the Nch differential pair (M11 and M12) and a high potential power supply VDD2. A positive polarity reference voltage V11 is applied to a gate of NMOS transistor M12, i.e., a non-inverting input terminal of the Nch differential pair (M11 and M12). A gate of NMOS transistor M11, i.e., an inverting input terminal of the Nch differential pair is connected to an output terminal N11 of the amplifier.
An amplifier stage of the positive polarity amplifier 210 includes an amplification transistor for charging M16 and an amplification transistor for discharging M18. The amplification transistor for charging M16 is connected between the high potential power supply VDD2 and the amplifier output terminal N11 and has a gate connected to an input end of the Pch current mirror (M13, M14), i.e., to a connection node between M12 and M14. The amplification transistor for discharging M18 is connected between the amplifier output terminal N11 and a intermediate voltage source VDD1.
The intermediate stage of the positive polarity amplifier 210 includes floating current sources M51 and M52 and current sources M53 and M54. The floating current source 51 includes a Pch transistor M51 that has gate supplied with the bias voltage BP1, has a source connected to the gate N13 of the amplification transistor M16 and has a drain connected to the gate terminal N15 of the amplification transistor M18. The floating current source M52 includes an Nch transistor M52 that has a gate supplied with a bias voltage BN1, has a drain connected to a gate terminal N13 of the amplification transistor M16 and has a source connected to a gate terminal N15 of the amplification transistor M18. The current source M53 is connected between a high voltage source VDD2 and the gate terminal N13 of the amplification transistor M16. The current source M54 is connected between the intermediate voltage source VDD1 and the gate terminal N15 of the amplification transistor M18. The sum current of the floating current sources M51 and M52 is set at a current approximately equal to each of the currents of the current sources M53 and M54.
A negative polarity amplifier 220 includes a differential input stage, an intermediate stage and an output stage. The differential input stage of the negative polarity amplifier 220 includes a current source M25 that has a first terminal connected to the high voltage source VDD2, and a Pch differential pair (M21 and M22) that has coupled sources connected to the second terminal of the current source M25, and an Nch current mirror (M23 and M24) connected between an output pair of the Nch differential pair (M21 and M22) and the low potential power supply VSS. A negative polarity reference voltage V21 is applied to a gate of the transistor M22, i.e., a non-inverting input terminal of the Pch differential pair (M21, M22). A gate of the transistor M21, i.e., an inverting input terminal of the Nch differential pair (the gate of M21) is connected to an output terminal N12 of the amplifier.
An amplifier stage of the negative polarity amplifier 220 includes an amplification transistor for discharging M26 and an amplification transistor for charging M28. The amplification transistor for discharging M26 is connected between the amplifier output terminal N12 and the low potential power supply VSS and has a gate connected to an input end (connection node of transistors M22 and M24) of the Nch current mirror (M23 and M24). The amplification transistor for charging M28 is connected between the intermediate voltage source VDD1 and the amplifier output terminal N12.
The intermediate stage of the negative polarity amplifier 220 includes floating current sources M61 and M62 and current sources M63 and M64. The floating current source 61 includes a Pch transistor M61 that has a gate supplied with the bias voltage BP2, has a drain connected to the gate terminal N14 of the amplification transistor M26 and has a source connected to the gate terminal N16 of the amplification transistor M28. The floating current source M62 includes an Nch transistor M62 that has a gate supplied with a bias voltage BN2, has a source connected to the gate terminal N14 of the amplification transistor M26 and has a drain connected to the gate terminal N16 of the amplification transistor M28. The current source M63 is connected between the intermediate voltage source VDD1 and the gate terminal N16 of the amplification transistor M28. The current source M64 is connected between a gate node N14 of the amplification transistor M26 and the low voltage source VSS. The sum current of the floating current sources M61 and M62 is set as a current approximately equal to each of the currents of the current sources M63 and M64.
The potential difference between the power supply voltages of the intermediate stage and the output stage of each of the positive polarity amplifier 210 and the negative polarity amplifier 220 is set to one-half of the potential difference of the power supply voltages of differential units 210A and 220A, respectively.
Since the major portion of current consumed in each of the positive polarity amplifier 210 and the negative polarity amplifier 220 flows through the output stage, the power consumption may be reduced to about one-half.
The arrangement of FIG. 9 also is a half-VDD amplifier. As compared to the power supply voltage range VDD2 to VSS of the differential stage of the positive polarity amplifier 210, the power supply voltage range VDD2 to VDD1 of the differential stage of the positive polarity amplifier is rather small. For example, VDD1=VDD2/2.
In the related art shown in FIG. 9, there is provided an auxiliary transistor M31 which operate to clamp the gate voltage of the output stage PMOS transistor M16 at VDD1 so that gate potential of the output stage PMOS transistor M16 will not be lower than VDD1. The reason for providing such auxiliary transistor M31 is that, since the withstand voltage of component elements of the output stage of the positive polarity amplifier 210 is to be lowered in correspondence with the power supply voltage range VDD2 to VDD1, a voltage beyond the withstand voltage is not to be applied to the elements. The auxiliary transistor M31 is connected between the gate of the PMOS transistor M16 and the power supply voltage VDD2, and has a gate supplied with a bias voltage VBN. There is also provided an auxiliary transistor M41 which operate to clamp the gate voltage of the output stage NMOS transistor M26 at VDD1 so that the gate potential of the output stage NMOS transistor will not be higher than VDD1. The reason for providing such auxiliary transistor M41 is that, since the withstand voltage of the component elements of the output stage of the negative polarity amplifier 220 is to be lowered in correspondence with the power supply voltage range VDD1 to VSS, a voltage beyond the withstand voltage is not to be applied to the elements. The auxiliary transistor M41 is connected between the gate of the output stage NMOS transistor M26 and the power supply VSS, and has a gate supplied with a bias voltage VBP.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2009-244830A (FIG. 6)    [Patent Document 2] JP Patent Kokai Publication No. JP-P2008-116654A (FIG. 4)